1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device which comprises a capacitor.
2. Description of the Related Art
Since semiconductor devices, such as DRAMs (Dynamic Random Access Memory), has been in a trend of high integration, also a capacitor structure has been formed into a 3D form and having a large thickness in order to realize a sufficiently large capacitance within a limited space.
FIGS. 10(a)-10(d) are cross sectional views sequentially showing an essential portion of steps of a method of manufacturing a conventional semiconductor device having a stacked type capacitor.
As shown in FIG. 10(a), an interlayer insulating film 9 in the form of a silicon oxide film is deposited on the overall surface of a silicon substrate 1.
Then, a usual photolithography technique and a usual reactive type ion etching technique are used to form, on the interlayer insulating film 9, a contact hole 9a which reaches the substrate 1.
Then, as shown in FIG. 10(b), polysilicon 15 is deposited on the interlayer insulating film 9 including the inside portion of the contact hole 9a.
After the polysilicon has been deposited, a resist is applied to the overall surface.
Then, a photomask different from that used when the contact hole 9a has been formed is used to perform a photolithography process so as to form the resist into a required shape. Thus, a mask 16 is formed.
Then, as shown in FIG. 10(c), a dry etching process is performed by using the resist mask 16 to form the polysilicon 15. Thus, a storage node (a lower electrode) 10 is formed.
Then, as shown in FIG. 10(d), a dielectric film 11 is formed on the surface of the storage node 10 by, for example, a CVD method. Then, for example, the CVD method is used to grow a polycrystal silicon film. Thus, a cell plate (an upper electrode) 12 is formed so that a stacked type capacitor 13 is formed. As a result, a method of manufacturing a semiconductor device is obtained.
However, the conventional method having the step of forming the contact hole 9a and the storage node 10 by using the individual mask patterns has a difficulty in stacking the contact hole 9a and the storage node 10 with a required accuracy because the structure has been fined considerably.
Since the capacitor 13 has the structure having a large thickness, a process in the direction of the depth cannot easily be performed.